FPGA architecture for fast parallel computation of co-occurrence matrices
نویسندگان
چکیده
منابع مشابه
FPGA architecture for fast parallel computation of co-occurrence matrices
This paper presents a novel architecture for fast parallel computation of cooccurrence matrices in high throughput image analysis applications for which time performance is critical. The architecture was implemented on a Xilinx Virtex-XCV2000E-6 FPGA using VHDL. The symmetry and sparseness of the co-occurrence matrices are exploited to achieve improved processing times, and smaller, flexible ar...
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EDSON PEDRO FERLIN† HEITOR SILVÉRIO LOPES§ CARLOS R. ERIG LIMA‡ MAURÍCIO PERRETTO♦ † Computer Engineering Department, Positivo University, R. Prof. Pedro V.P. de Souza, 5300, 81280-330 Curitiba (PR), Brazil †[email protected], ♦[email protected] § Bioinformatics Laboratory, Federal University of Technology – Paraná, Av. 7 de setembro, 3165, 80230-901 Curitiba (PR), Brazil §[email protected]...
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ژورنال
عنوان ژورنال: Microprocessors and Microsystems
سال: 2007
ISSN: 0141-9331
DOI: 10.1016/j.micpro.2006.02.013